1. Technical Field of the Invention
The present invention relates to the overhead (OH) bytes of synchronous optical networks such as Synchronized Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) telecommunication standards.
2. Background of the Invention
Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) are closely related standards for transporting digital information over optical fiber using lasers or Light Emitting Diodes (LEDs). In synchronous optical networking, the payload and overhead of the frame are transmitted through interleaving, with a portion of the overhead being transmitted, then a portion of the payload, then another portion of the overhead, etc., until the entire frame has been transmitted. In both SONET and SDH the entire frame is transmitted in 125 microseconds; the SONET frame totals 810 octets in size, 27 octets of overhead with 783 octets of payload, while the SDH frame totals 2430 octets in size, 81 octets of overhead with 2349 octets of payload.
The fundamental components of a synchronous optical networking frame include the Synchronous Payload Envelope (SPE) and the Transport Overhead (TOH), which includes the Section Overhead (SOH) and Line Overhead (LOH). The present invention relates to such OH, which includes bytes H1, H2, H3, B1, B2, J0, J1, etc. Below, the “Second Illustrative Embodiment of the Present Invention” demonstrates the “Context-Sensitive Overhead Processor” (CSOP) operating on the H1/H2 pointer pair for explanative purposes; therefore, a general background of the H1/H2 pointer pair is provided.
The pointer mechanism channels are found in bytes H1/H2/H3, which are located in the fourth row and first three columns of a SONET/SDH frame (see FIG. 1). In SONET, the H1/H2 bytes are responsible for identifying the beginning of the SPE (J1) at all times, while in SDH, the H1/H2/H3 bytes comprise the Administrative Unit (AU), which may point to three distinct Tributary Units (TUs). The H1/H2 bytes must always identify the first byte of the Path Overhead (POH), which is the first byte of the SPE: in SONET the first byte is referred to as the Virtual Tributary (VT), identified by the TU-3 pointer; in SDH the first byte is referred to as the Virtual Container (VC), identified by the AU-3 or AU-4 pointers. Due to jitter and/or other timing factors, the start of the SPE may move within the payload envelope; therefore, the pointer bytes provide a mechanism for the sender to inform the receiver where the individual data containers of the SPE are located at all times. The New Data Flag (NDF), contained within the H1/H2 bytes, permits the pointer position to change in response to a move in the position of the payload, and the H3, or pointer action byte, compensates for timing changes in the payload by providing negative or positive timing adjustments through holding stuff bytes, when necessary. The H1/H2 bytes indicate when the H3 byte carries value. The interaction of the H1/H2/H3 bytes therefore provides the ability for high speed transmission of frames over the synchronous network without the addition of large buffers.
In SONET/SDH synchronous optical networking, the H1/H2 bytes adhere to strict pointer rules; the structure of the H1 byte is always NNNNSSID and the structure of the H2 byte is always IDIDIDID. The “N” bits in the H1 bytes constitute the NDF, which for normal pointer operation, are set to a value of 0110. A NDF value of 1001 indicates the previous pointer was incorrect, and the receiver is to use the new pointer indicated in the IDIDIDIDID field(s). If the received bit configurations are not “1001” or “0110” the “three of four rule” is used; 1110 is interpreted as 0110, 1101 is interpreted as 1001, etc. The next 2 bits in the H1 byte (SS) have no value in SONET, but are reserved as place keepers with a “00” value. These bits formerly carried sizing and mapping information, which are now located elsewhere SDH still assigns value to the S bits, normally “10” for both AU-3 and AU-4.
The last 2 bits of the H1 byte, combined with the 8 bits in the H2 byte, form the pointer to the SPE located in J1. These IDIDIDIDID bits are used to indicate the type of adjustment(s) that may be required if the SPE has moved. If a positive pointer adjustment is about to occur, the “I” bits invert the pointer value that has been received for a period of 1 frame, with the second frame containing the new value and the pointer adjustment. If a negative pointer adjustment is about to occur, the “D” bits invert the pointer value that has been received for a period of 1 frame, with the second frame containing the new value and the pointer adjustment. In order for the new pointer to be counted as valid, the new pointer must be maintained for at least 3 frames.
While processing of the H1/H2 pointer pair is explored in the “Second Illustrative Embodiment of the Present Invention,” as a means of further demonstrating the present invention, it is important to note that this embodiment of the invention is not intended to be restrictive, for the present invention is constructed to operate on all OH bytes, including B1, B2, J0, J1, etc., and can therefore be performed in multiple embodiments.
The present invention increases and therefore improves the rate of data transmission found in the prior art through reducing the number of OH processors required in synchronous optical network transmission to the number of bytes in a datapath. Unlike some prior overhead processors, the present invention does not require the use of a substitution element. In addition, the present invention differs from prior art by employing multiple flip-flops, located on the path from the logic element to the elastic store (4), and on the path from the elastic store to the logic element (5); such flip-flops break up the pathways between the elastic store and the logic element, allowing the data to be transmitted faster, and resulting in the ability for both the previous OH context and next OH context to be transmitted simultaneously, in one clock cycle, requiring half of the time necessary in the prior art. In addition, the latency from an elastic store, such as a RAM, is higher than the latency from a flip flop; thus by employing flip-flops along the pathway between the logic element to the elastic store, as well as the pathway between the elastic store and the logic element, the present invention is able to reduce the latency of the system.